Job Description

Job Title: Design Verification Engineer
Location: Milpitas, CA
Description:

Primary Responsibilities Include:
\xef\x82\xb7 Responsible for all aspects of verification methodology employed and for
ensuring the application of uniform standards and adoption of best practices.
\xef\x82\xb7 Work and liaison with other Design Verification teams within our customer
sites to identify holes in the design verification flow and implement
corrective action.
\xef\x82\xb7 Overall, responsible for verification of ASIC designs To include
such things as:
o Design Verification \xe2\x80\x93 Implement test benches in UVM and Sytem
Verilog, run regressions at RTL and gate level, generate and report DV
metrics with respect to bug tracking and code coverage, debug
failures and provide feedback to the design team.
o Responsible for oversight and completion of debugging problems and
troubleshooting in Real Time. This includes being responsible for
Debugging Designs for High throughput, Low Latency of Pipeline and
Dynamic Power Management at full system level.
o Setup Verification Regression suites at RTL Level & Corresponding
Netlist Level after Synthesis to test any/all Corner case conditions.
\xef\x82\xb7 Work closely with Socionext\xe2\x80\x99s design team to ensure the Company is meeting
design requirements for projects. This may include: review of specifications,
understanding chip architecture, developing tests & coverage plans, and
defining methodology & test benches.
\xef\x82\xb7 Work closely with Socionext\xe2\x80\x99s Custom SoC department to provide great
customer service to our clients and the projects at hand. Support, encourage
and drive timely and accurate deliverables with customers within schedules

Necessary Qualifications:
\xef\x82\xb7 BS or MS in Computer Science or Electrical Engineering.
\xef\x82\xb7 5-10+ years of industry experience bringing silicon ICs into high volume
production.
\xef\x82\xb7 Must have strong experience with UVM.
\xef\x82\xb7 Must have a full chip verification experience
\xef\x82\xb7 Experience of leading a single project.
\xef\x82\xb7 Knowledge of industry standard interfaces. Extensive Familiarity with
Verilog, Simulation tools & demonstrated ability to debug Problems &
Troubleshoot in Real Time.
\xef\x82\xb7 Sound knowledge of ARMv8, interconnect, memory coherence and memory
architectures
\xef\x82\xb7 Familiarity with Formality & most popular Verification Tools. (Key
knowledge should include such topics as: IP validation, Gate level
verification, FPGA Validation, Emulation, Silicon Validation, Reference Board
bring up verification, Silicon Bring up, DFx, Low Power Verification)
\xef\x82\xb7 Expertise in writing Perl / Python , awk, sed & Common Scripts to automate
the Verification Tasks for CPU plus all Chip peripherals \xe2\x80\x93 USB, PCIe, MIPI,
SDIO, PCI E & DDR Controllers.
\xef\x82\xb7 Advanced knowledge of ASIC design and verification flow including RTL
design, simulation, test bench development, regression, equivalence
checking, timing analysis, scan insertion and test pattern generation
\xef\x82\xb7 Experience with low-level programming of systems in C/C++.
\xef\x82\xb7 Experienced in writing scripts in languages such as Perl, Python, and Tcl.
\xef\x82\xb7 Functional understanding of constrained random verification process,
functional coverage, and code coverage.
\xef\x82\xb7 Low power verification UPF
\xef\x82\xb7 Team player with excellent communication skills and the desire to take on
diverse challenges.
\xef\x82\xb7 Customer interaction

Other Qualifications:
\xef\x82\xb7 Good knowledge of low power camera and imaging systems is a plus
\xef\x82\xb7 Experience with formal verification tools is a plus.
\xef\x82\xb7 CPU Security, Secure boot, Secure JTAG
\xef\x82\xb7 Familiarity with ARM architecture
\xef\x82\xb7 Familiarity with scripting/programming with Perl/Python, Tcl, C/C++

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